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Researchers at IBM Quantum have introduced SVD stacking, a technique that reduces the complexity of calibrating high-fidelity quantum gates by identifying low-dimensional subspaces within pulse-parameter spaces. This approach streamlines on-device optimization for fault-tolerant computing by focusing calibration efforts on manageable parameter sets while maintaining resilience against amplitude, detuning, and coherent errors.
A new technique simplifies designing high-fidelity quantum gates
Designing precise, high-fidelity quantum gates is crucial for quantum computing, but calibrating complex control pulses remains difficult.
Researchers at IBM Quantum and collaborating institutions have streamlined the design of high-fidelity quantum gates using a technique called SVD stacking. This method reduces the complexity of calibrating quantum gates by lowering the dimensionality of the parameter spaces used in optimization. The team successfully designed and calibrated an Xπ/2 gate resilient to both amplitude and detuning errors, and a separate Xπ/2 gate robust against coherent errors caused by a spectator qubit. This work, dated August 26, 2026, offers a pathway toward more efficient on-device optimization for fault-tolerant quantum computing. Identifying a low-dimensional subspace within the high-dimensional pulse-parameter space is now possible through a new approach, restricting pulse variations during on-device gate calibration. The technique successfully limits the…
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